Verilog

MTech Verilog Projects
Following are the list of of topics on which we can provide you the dissertation. Kindly choose your preference and inform us accordingly.
 Schematic and Layout Design of low power flip flop
 VLSI design & FPGA Implementation of “Area-Efficient 3-Input Decimal Adders Using Simplified Carry and Sum Vectors”
 VLSI design & FPGA Implementation of “A Pipelined 8BIOB Encoder for a High speed SerDes”
 VLSI design & FPGA Implementation of “Faster and Energy-Efficient Signed Multipliers”
 VLSI design & FPGA Implementation of “high speed & area efficient booth multiplier
 VLSI design & FPGA Implementation of ” Bus encoder for crosstalk avoidance in RLC modelled interconnects”
 VLSI design & FPGA Implementation of “Design of High Speed 32 Bit Truncation-Error-Tolerant Adder”
 VLSI design & FPGA Implementation of “New Approach for Implementing BCD Adder Using Flagged Logic”
 VLSI design & FPGA Implementation of “Design and Synthesis of Reversible Fault Tolerant Carry Skip Adder/Subtractor”
 Design and Implementation of an FPGA-based Real-Time Face Recognition System
 Design and Implementation of Low Power Digital FIR Filter based on low power multipliers and adders on xilinx FPGA
 Design and Implementation of USB 2.0 Transceiver Macro-cell Interface (UTMI) (2010)
 Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm
 Design of adiabatic 32 bit multiplier using modified booth algorithm
 Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
 Design of Data Encryption Standard (DES)
 VLSI design & FPGA Implementation of ” Design of Approximate Multiplier for Error-Tolerant Applications” .
 VLSI design & FPGA Implementation of ” Design and Synthesis of Bus Invert Encoding and Decoding Technique Using Reversible Logic.
 VLSI design & FPGA Implementation of “Delay Comparison of 4 by 4 Vedic Multiplier based on Different Adder Architectures using VHDL”
 VLSI design & FPGA Implementation of “Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces” .
 Vehicle speed checker & vehicle identification” .
 VLSI design & FPGA Implementation of “high speed 4-Input Decimal Adders Using Simplified Carry and Sum Vectors” (IEEE)
 VLSI design & FPGA Implementation of “high speed 5-Input Decimal Adders Using Simplified Carry and Sum Vectors” (IEEE)
 VLSI design & FPGA Implementation of “Faster and Energy-Efficient 64 bit a new Signed Multipliers” .
 Design of Ultra low power full adder
 Digital Image Authentication from JPEG Headers
 Feature Extraction of Digital Aerial Images by FPGA based implementation of edge detection algorithms
 FPGA based FFT Algorithm Implementation in WiMAX Communications System
 FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical Imaging
 FPGA Implementation of a Scalable Encryption Algorithm
 Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA
 Low-Power and Area-Efficient Carry Select Adder
 VLSI design & FPGA Implementation of ” A New Bus encoder for crosstalk avoidance in RLC modelled interconnects”.
 VLSI design & FPGA Implementation of “Novel Approach To 32 Bit Truncation-Approximate Adder” .
 VLSI design & FPGA Implementation of “A New Approach for BCD Adder and design a high speed 64 bit decimal adder”
 VLSI design & FPGA Implementation of ” Design of Approximate signed Multiplier for Error-Tolerant Applications” .
 VLSI design & FPGA Implementation of ” Design and Synthesis of Bus Invert Encoding and Decoding Technique Using a new proposed Reversible Logic”
 VLSI design & FPGA Implementation of “Design a Vedic Multiplier Architectures using VHDL”.
 A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop
 Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates
 Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
 Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme IEEE
 A High-speed 32-bit Signed/Unsigned Pipelined Multiplier
 A Low-Power Multiplier With the Spurious Power Suppression Technique
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