VLSI Projects for PhD

Following are the list of of topics on which we can provide you the dissertation. Kindly choose your preference and inform us accordingly.

- A Modified Partial Product Generator for Redundant Binary Multipliers
- Area and Frequency optimized 1024 point Radix-2 FFT Processor on FPGA
- Design & Analysis of 16 bit RISC Processor Using low Power Pipelining
- Design and Analysis of Approximate Compressors for Multiplication
- Design and Implementation of 16 x 16 Multiplier Using Vedic Mathematics
- Design and implementation of fast floating point multiplier unit
- Design and Simulation of Single Layered Logic Generator Block using Quantum Dot Cellular Automata
- Design of Area and Power Aware Reduced Complexity Wallace Tree Multiplier
- Design of Area and Power Efficient Digital FIR Filter Using Modified MAC Unit
- Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder
- Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications
- FPGA Implementation of Scalable Microprogrammed FIR Filter Architectures using Wallace Tree and Vedic Multipliers
- A BIST TPG for Low Power Dissipation and High Fault Coverage
- VLSI Implementation of UART with BIST capability
- FPGA implementation JPEG 2000 using 2-D DWT
- FPGA implementation of the REDEYE detection and correction
- VLSI design & FPGA Implementation of ” Bus encoder for crosstalk avoidance in RLC modelled interconnects”
- VLSI design & FPGA Implementation of ” Design and Synthesis of Bus Invert Encoding and
- VLSI design & FPGA Implementation of “Area-Efficient 3-Input Decimal Adders Using Simplified Carry and Sum Vectors”
- VLSI design & FPGA Implementation of “New Approach for Implementing BCD Adder Using Flagged Logic”
- A High-Speed FPGA Implementation of an RSD-Based ECC Processor
- A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM
- Advanced Low Power RISC Processor Design using MIPS Instruction Set
- An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
- Analysis of Ternary Multiplier using Booth Encoding Technique
- “Decoding Technique Using Reversible Logic VLSI design & FPGA Implementation of “”Delay Comparison of 4 by 4 Vedic Multiplier
- based on Different Adder Architectures using VHDL”””
- Design & Analysis of 16 bit RISC ProcessorUsing low Power Pipelining
- Design of low power and high speed Carry Select Adder using Brent Kung adder
- Design of low power and high speed Carry Select Adder using Brent Kung adder
- FPGA based Scalable Fixed Point QRD core using Dynamic Partial Reconfiguration
- FPGA implementation of LDPC bit-flipping algorithm using Co-simulation.
- FPGA implementation of LDPC bit-flipping algorithm using Co-simulation.
- FPGA implementation of LDPC Decoder using min-sum algorithm.
- FPGA implementation of the 12-bit Ternary multiplier.
- ” VLSI design & FPGA Implementation of “” Design and Synthesis of Bus Invert Encoding and Decoding Technique
- Using a new proposed Reversible Logic”””
- VLSI design & FPGA Implementation of ” Design of Approximate signed Multiplier for Error-Tolerant Applications” .
- VLSI design & FPGA Implementation of “A New Approach for BCD Adder and design a high speed 64 bit decimal adder”
- VLSI design & FPGA Implementation of “Design a Vedic Multiplier Architectures using VHDL”
- . Design of low power test pattern generator
- A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits
- A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM
- Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
- Area and frequency optimized 1024 point Radix-2 FFT processor on FPGA
- Design & Analysis of 16 bit RISC ProcessorUsing low Power Pipelining
- Design and Implementation of 10/100 Mbps (Mega bits per second) Ethernet Switch for Network applications (2010)
- Design and Implementation of USB 2.0 Transceiver Macro-cell Interface (UTMI) (2010)
- Design of ECG signal processing and denoising using co-simulation.
- FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers
- FPGA implementation of the 12-bit Ternary multiplier.
- FPGA implementation of the REDEYE detection and correction
- FPGA realization and performance evaluation of fixedwidth modified Baugh-Wooley multiplier
- FPGA Realization and Performance Evaluation of Fixed-Width Modified Baugh-Wooley Multiplier
- High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols
- High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
- HMFPCC: – Hybrid-Mode Floating Point Conversion Co-processor
- Implementation of AES for image encryption and decryption
- Implementation of AES for image encryption and decryption.
- Intelligent and Adaptive Traffic Light Controller (IA-TLC) using FPGA
- Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
- Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
- Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications
- On the Analysis of Reversible Booth’s Multiplier
- Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
- Reverse Converter Design via Parallel-Prefix Adders:Novel Components, Methodology, and Implementations
- Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI
- RTL Implementation for AMBA ASB APB Protocol at System on Chip Level
- Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications
- Technology Optimized Fixed-Point Bit-Parallel Multiplier for LUT based FPGAs
- Truncated ternary multipliers
- Vehicle speed checker & vehicle identification”
- VLSI design & FPGA Implementation of “A Pipelined 8BIOB Encoder for a High speed SerDes”
- VLSI design & FPGA Implementation of ” A New Bus encoder for crosstalk avoidance in RLC modelled interconnects”.
- VLSI design & FPGA Implementation of ” Design of Approximate Multiplier for Error-Tolerant Applications” .
- “VLSI design & FPGA Implementation of “”Absolute Difference and Low-Power Bus
- Encoding Method for LCD Digital Display Interfaces”” .”
- VLSI design & FPGA Implementation of “Design and Synthesis of Reversible Fault Tolerant Carry Skip Adder/Subtractor”
- VLSI design & FPGA Implementation of “Design of High Speed 32 Bit Truncation-Error-Tolerant Adder”
- VLSI design & FPGA Implementation of “Faster and Energy-Efficient 64 bit a new Signed Multipliers” .
- VLSI design & FPGA Implementation of “Faster and Energy-Efficient Signed Multipliers”
- VLSI design & FPGA Implementation of “high speed & area efficient booth multiplier
- VLSI design & FPGA Implementation of “high speed 4-Input Decimal Adders Using Simplified Carry and Sum Vectors” (IEEE)
- VLSI design & FPGA Implementation of “high speed 5-Input Decimal Adders Using Simplified Carry and Sum Vectors” (IEEE)
- VLSI design & FPGA Implementation of “Novel Approach To 32 Bit Truncation-Approximate Adder” .
- VLSI implementation of 64, 32, 16 and 8 bit CSA
- VLSI implementation of Decimal to binary conversion
- VLSI implementation of RSA cryptography algorithm
- A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique (2010)
- Design and Implementation of Digital low power base band processor for RFID Tags (2010)
- Design and Implementation of Reversible Watermarking for JPEG2000 Standard
- FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical Imaging
- Design and Implementation of High Speed DDR SDRAM (Dual Data Rate Synchronously Dynamic RAM) Controller (2010)
- Design and Implementation of Lossless DWT/IDWT for Medical Images
- High Performance Complex Number Multiplier Using Booth-Wallace Algorithm
- High Speed Parallel CRC Implementation Based On Unfolding, Pipelining and Retiming
- Design of an Bus Bridge between OCP and AHB Protocol (2010)
- Design of Gigabit Ethernet MAC (Medium Access Control) Transmitter
- Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
- Design of Data Encryption Standard (DES)
- Design of Distributed Arithmetic FIR Filter
- Design of Universal Asynchronous Receiver Transmitter (UART)
- Design of Triple Data Encryption Standard (DES)
- Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm
- Design of Dual Elevator Controller
- Design of an ATM (Automated Teller Machine) Controller
- Design of 8-Bit Pico Processor (VHDL)
- Design of JPEG Image compression standard
- Design of Digital FM Receiver using PLL (Phase Locked Loop)
- Design of 16-bit QPSK (Quadrature Phase Shift Keying)
- Design of 16-bit QAM (Quadrature Amplitude Modulation) Modulator
- Design of AES (Advanced Encryption Standard) Encryption Algorithm with 128- bits Key Length
- Design of RS-232 System Controller
- Design of CRC (Cyclic Redundancy Check) Generator (VLSI)
- Design and Implementation of OFDM Transmitter (VHDL)
- Design of 8-bit Microcontroller (VHDL)
- A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
- An Efficient Architecture for 3-D Discrete Wavelet Transform
- The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation
- Design of On-Chip Bus with OCP Interface
- Design of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix.
- Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms
- An Efficient Architecture for 2-D Lifting-based Discrete Wavelet Transform
- Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers
- A Spurious-Power Suppression Technique for Multimedia/DSP Applications
- Design of AES (Advanced Encryption Standard) Encryption and Decryption Algorithm with 128-bits Key Length
- DDR3 based lookup circuit for high-performance network processing
- Multiplication Acceleration Through Twin Precision 32-bit RISC CPU Based on MIPS
- High Speed Hardware Implementation of 1D DCT/IDCT
- Efficient FPGA implementation of convolution
- High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures
- Implementation of a visible Watermarking in a secure still digital Camera using VLSI design
- Implementation of FFT/IFFT Blocks for OFDM
- Design and Implementation of Efficient Systolic Array Architecture for DWT (Discrete Wavelet Transform)

We provide guidance for MTech students in VLSI, VLSI thesis, IEEE VLSI Projects, VLSI IEEE Projects, final year VLSI MTech Projects, RTU Mtech Projects, RTU VLSI Thesis, RTU Projects, VLSI MS Projects, VLSI BE Projects, VLSI BTech Projects, VLSI ME Projects, VLSI project for RTU, IEEE Basepapers of VLSI, VLSI Final Year Projects, VLSI Projects,VLSI Academic Projects, VLSI Free Download Projects, VLSI Seminar Topics, VLSI Free Projects in Jaipur, Ajmer, Kota,Delhi, Faridabad, banglore, lacknow,India.

MTech VLSI Projects

Following are the list of of topics on which we can provide you the dissertation. Kindly choose your preference and inform us accordingly.

- A Modified Partial Product Generator for Redundant Binary Multipliers
- Area and Frequency optimized 1024 point Radix-2 FFT Processor on FPGA
- Design & Analysis of 16 bit RISC Processor Using low Power Pipelining
- Design and Analysis of Approximate Compressors for Multiplication
- Design and Implementation of 16 x 16 Multiplier Using Vedic Mathematics
- Design and implementation of fast floating point multiplier unit
- Design and Simulation of Single Layered Logic Generator Block using Quantum Dot Cellular Automata
- Design of Area and Power Aware Reduced Complexity Wallace Tree Multiplier
- Design of Area and Power Efficient Digital FIR Filter Using Modified MAC Unit
- Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder
- Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications
- FPGA Implementation of Scalable Microprogrammed FIR Filter Architectures using Wallace Tree and Vedic Multipliers
- A BIST TPG for Low Power Dissipation and High Fault Coverage
- VLSI Implementation of UART with BIST capability
- FPGA implementation JPEG 2000 using 2-D DWT
- FPGA implementation of the REDEYE detection and correction
- VLSI design & FPGA Implementation of ” Bus encoder for crosstalk avoidance in RLC modelled interconnects”
- VLSI design & FPGA Implementation of ” Design and Synthesis of Bus Invert Encoding and
- VLSI design & FPGA Implementation of “Area-Efficient 3-Input Decimal Adders Using Simplified Carry and Sum Vectors”
- VLSI design & FPGA Implementation of “New Approach for Implementing BCD Adder Using Flagged Logic”
- A High-Speed FPGA Implementation of an RSD-Based ECC Processor
- A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM
- Advanced Low Power RISC Processor Design using MIPS Instruction Set
- An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
- Analysis of Ternary Multiplier using Booth Encoding Technique
- “Decoding Technique Using Reversible Logic VLSI design & FPGA Implementation of “”Delay Comparison of 4 by 4 Vedic Multiplier
- based on Different Adder Architectures using VHDL”””
- Design & Analysis of 16 bit RISC ProcessorUsing low Power Pipelining
- Design of low power and high speed Carry Select Adder using Brent Kung adder
- Design of low power and high speed Carry Select Adder using Brent Kung adder
- FPGA based Scalable Fixed Point QRD core using Dynamic Partial Reconfiguration
- FPGA implementation of LDPC bit-flipping algorithm using Co-simulation.
- FPGA implementation of LDPC bit-flipping algorithm using Co-simulation.
- FPGA implementation of LDPC Decoder using min-sum algorithm.
- FPGA implementation of the 12-bit Ternary multiplier.
- ” VLSI design & FPGA Implementation of “” Design and Synthesis of Bus Invert Encoding and Decoding Technique
- Using a new proposed Reversible Logic”””
- VLSI design & FPGA Implementation of ” Design of Approximate signed Multiplier for Error-Tolerant Applications” .
- VLSI design & FPGA Implementation of “A New Approach for BCD Adder and design a high speed 64 bit decimal adder”
- VLSI design & FPGA Implementation of “Design a Vedic Multiplier Architectures using VHDL”
- . Design of low power test pattern generator
- A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits
- A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM
- Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
- Area and frequency optimized 1024 point Radix-2 FFT processor on FPGA
- Design & Analysis of 16 bit RISC ProcessorUsing low Power Pipelining
- Design and Implementation of 10/100 Mbps (Mega bits per second) Ethernet Switch for Network applications (2010)
- Design and Implementation of USB 2.0 Transceiver Macro-cell Interface (UTMI) (2010)
- Design of ECG signal processing and denoising using co-simulation.
- FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers
- FPGA implementation of the 12-bit Ternary multiplier.
- FPGA implementation of the REDEYE detection and correction
- FPGA realization and performance evaluation of fixedwidth modified Baugh-Wooley multiplier
- FPGA Realization and Performance Evaluation of Fixed-Width Modified Baugh-Wooley Multiplier
- High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols
- High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
- HMFPCC: – Hybrid-Mode Floating Point Conversion Co-processor
- Implementation of AES for image encryption and decryption
- Implementation of AES for image encryption and decryption.
- Intelligent and Adaptive Traffic Light Controller (IA-TLC) using FPGA
- Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
- Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
- Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications
- On the Analysis of Reversible Booth’s Multiplier
- Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
- Reverse Converter Design via Parallel-Prefix Adders:Novel Components, Methodology, and Implementations
- Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI
- RTL Implementation for AMBA ASB APB Protocol at System on Chip Level
- Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications
- Technology Optimized Fixed-Point Bit-Parallel Multiplier for LUT based FPGAs
- Truncated ternary multipliers
- Vehicle speed checker & vehicle identification”
- VLSI design & FPGA Implementation of “A Pipelined 8BIOB Encoder for a High speed SerDes”
- VLSI design & FPGA Implementation of ” A New Bus encoder for crosstalk avoidance in RLC modelled interconnects”.
- VLSI design & FPGA Implementation of ” Design of Approximate Multiplier for Error-Tolerant Applications” .
- “VLSI design & FPGA Implementation of “”Absolute Difference and Low-Power Bus
- Encoding Method for LCD Digital Display Interfaces”” .”
- VLSI design & FPGA Implementation of “Design and Synthesis of Reversible Fault Tolerant Carry Skip Adder/Subtractor”
- VLSI design & FPGA Implementation of “Design of High Speed 32 Bit Truncation-Error-Tolerant Adder”
- VLSI design & FPGA Implementation of “Faster and Energy-Efficient 64 bit a new Signed Multipliers” .
- VLSI design & FPGA Implementation of “Faster and Energy-Efficient Signed Multipliers”
- VLSI design & FPGA Implementation of “high speed & area efficient booth multiplier
- VLSI design & FPGA Implementation of “high speed 4-Input Decimal Adders Using Simplified Carry and Sum Vectors” (IEEE)
- VLSI design & FPGA Implementation of “high speed 5-Input Decimal Adders Using Simplified Carry and Sum Vectors” (IEEE)
- VLSI design & FPGA Implementation of “Novel Approach To 32 Bit Truncation-Approximate Adder” .
- VLSI implementation of 64, 32, 16 and 8 bit CSA
- VLSI implementation of Decimal to binary conversion
- VLSI implementation of RSA cryptography algorithm
- A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique (2010)
- Design and Implementation of Digital low power base band processor for RFID Tags (2010)
- Design and Implementation of Reversible Watermarking for JPEG2000 Standard
- FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical Imaging
- Design and Implementation of High Speed DDR SDRAM (Dual Data Rate Synchronously Dynamic RAM) Controller (2010)
- Design and Implementation of Lossless DWT/IDWT for Medical Images
- High Performance Complex Number Multiplier Using Booth-Wallace Algorithm
- High Speed Parallel CRC Implementation Based On Unfolding, Pipelining and Retiming
- Design of an Bus Bridge between OCP and AHB Protocol (2010)
- Design of Gigabit Ethernet MAC (Medium Access Control) Transmitter
- Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
- Design of Data Encryption Standard (DES)
- Design of Distributed Arithmetic FIR Filter
- Design of Universal Asynchronous Receiver Transmitter (UART)
- Design of Triple Data Encryption Standard (DES)
- Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm
- Design of Dual Elevator Controller
- Design of an ATM (Automated Teller Machine) Controller
- Design of 8-Bit Pico Processor (VHDL)
- Design of JPEG Image compression standard
- Design of Digital FM Receiver using PLL (Phase Locked Loop)
- Design of 16-bit QPSK (Quadrature Phase Shift Keying)
- Design of 16-bit QAM (Quadrature Amplitude Modulation) Modulator
- Design of AES (Advanced Encryption Standard) Encryption Algorithm with 128- bits Key Length
- Design of RS-232 System Controller
- Design of CRC (Cyclic Redundancy Check) Generator (VLSI)
- Design and Implementation of OFDM Transmitter (VHDL)
- Design of 8-bit Microcontroller (VHDL)
- A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
- An Efficient Architecture for 3-D Discrete Wavelet Transform
- The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation
- Design of On-Chip Bus with OCP Interface
- Design of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix.
- Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms
- An Efficient Architecture for 2-D Lifting-based Discrete Wavelet Transform
- Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers
- A Spurious-Power Suppression Technique for Multimedia/DSP Applications
- Design of AES (Advanced Encryption Standard) Encryption and Decryption Algorithm with 128-bits Key Length
- DDR3 based lookup circuit for high-performance network processing
- Multiplication Acceleration Through Twin Precision 32-bit RISC CPU Based on MIPS
- High Speed Hardware Implementation of 1D DCT/IDCT
- Efficient FPGA implementation of convolution
- High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures
- Implementation of a visible Watermarking in a secure still digital Camera using VLSI design
- Implementation of FFT/IFFT Blocks for OFDM
- Design and Implementation of Efficient Systolic Array Architecture for DWT (Discrete Wavelet Transform)

We provide guidance for MTech students in VLSI, VLSI thesis, IEEE VLSI Projects, VLSI IEEE Projects, final year VLSI MTech Projects, RTU Mtech Projects, RTU VLSI Thesis, RTU Projects, VLSI MS Projects, VLSI BE Projects, VLSI BTech Projects, VLSI ME Projects, VLSI project for RTU, IEEE Basepapers of VLSI, VLSI Final Year Projects, VLSI Projects,VLSI Academic Projects, VLSI Free Download Projects, VLSI Seminar Topics, VLSI Free Projects in Jaipur, Ajmer, Kota,Delhi, Faridabad, banglore, lacknow,India.